1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and in particular, to a dynamic random access memory (DRAM) and a manufacturing method of the same.
2. Description of the Background Art
Owing to remarkable spread of information equipments such as a computer, demand for semiconductor memory devices has been rapidly increased. In particular, semiconductor devices having such functional features as large-scale memory capacities and high-speed operations have been demanded. Correspondingly, technical development has been progressed for high integration, high-speed responsibility and high reliability of the semiconductor memory devices.
Among the semiconductor memory devices, a DRAM (dynamic random access memory) has been known as a device capable of random input and output of memory information. In general, the DRAM is formed of a memory cell array, which is a memory region storing a large amount of information, and a peripheral circuitry required for external input and output.
FIG. 34 is a block diagram showing a construction of a conventional DRAM. Referring to FIG. 34, a DRAM 150 includes a memory cell array 151 for storing data signals of memory information, a row and column address buffer 152 for externally receiving an address signal which is used for selecting the memory cell forming a unit memory circuit, row and column decoders 153 and 154 which decode the address signal o designate the memory cell, a sense refresh amplifier 155 which amplifies the signal stored in the designated memory cell to read the same, data-in and data-out buffers 156 and 157 for data input and data output, and a clock generator 158 for generating a clock signal.
The memory cell array 151 occupying a large area in the semiconductor chip is formed of a plurality of memory cells for storing unit memory information disposed in a matrix form. FIG. 35 is an equivalent circuit diagram showing memory cells for 4 bits forming the memory cell array 151. Each memory cell is formed of one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. Such memory cell is referred to as a memory cell of one-transistor and one-capacitor type. The memory cells of this type have simple structures and the degree of integration of the memory cell array can be easily increased, so that they have been widely used in DRAMs of large capacities.
The memory cells of the DRAMs can be classified into several types based on their structures of the capacitors. Among several types of the capacitors, a stacked type capacitor has such a feature that a major part of the capacitor may be extended over a gate electrode and a field isolating film, so that areas of opposed surfaces of electrodes of the capacitor can be increased and thus the capacitor capacitance can be increased. Since the stacked type capacitor has the foregoing feature, a sufficient capacitor capacitance can be ensured even if elements are miniaturized to a higher degree in accordance with the high integration of the semiconductor device. As a result, stacked type capacitors have been widely used in accordance with the high integration of the semiconductor devices. The semiconductor devices are now being further integrated, and the stacked type capacitors complying with it are now being developed. More specifically, a stacked type capacitor of a cylindrical form, which is intended to ensure an appropriate capacitor capacitance even if the semiconductor device is further integrated and thus has further miniaturized elements, has been proposed, e.g., Japanese Patent Application No. 02-89869 (1990).
FIG. 36 is a plan showing a conventionally proposed DRAM provided with cylindrical stacked type capacitors. FIG. 37 is a cross section of the DRAM taken along line X--X in FIG. 36.
Referring to FIGS. 36 and 37, the proposed DRAM in the prior art includes a silicon substrate 201, an element isolating oxide film 202 formed on a predetermined region of a major surface of the silicon substrate 201 for isolating elements, source/drain regions 206a, 206b, 206c and 206d, which are formed in regions surrounded by the element isolating oxide film 202 with predetermined spaces therebetween and are Located at opposite sides of a channel region 220, gate electrodes 204b and 204c formed on the channel regions 220 with gate oxide films 205 therebetween, word lines (gate electrodes) 204d and 204e formed on the element isolating oxide film 202 with a predetermined space therebetween, and insulating films 207 covering the gale electrodes 204b, 204c, 204d and 204e. The source/drain regions 206a and 206b and the gate electrode 204c form a transfer gate transistor 203 of one of the memory cells. The source/drain regions 206a and 206c and the gate electrode 204b form the transfer gate transistor 203 of the other memory cell.
The proposed DPAM in the prior art further includes a buried bit line 208 electrically connected to the source/drain region 206a, an insulating film 209 covering the buried bit line 208, a base portion 211a forming a storage node (capacitor lower electrode) 211 which is electrically connected to the source/drain region 206b and extends over the insulating films 207 and 209, a standing wall portion 211b which is formed on the base portion 211a and extends perpendicularly to the silicon substrate 201 from the outermost edge of the .base portion 211a for forming the storage node 211, a capacitor insulating film 212 covering the base portion 211a and the standing wall portion 211b, a cell plate 213 (capacitor upper electrode) covering the capacitor insulating film 212, an interlayer insulating film 214 covering the cell plate 213 and having a flat surface, interconnection layers 215 formed on the interlayer insulating film 214 and corresponding to the gate electrodes 204b, 204c, 204d and 204e, respectively, and a protection film 216 covering the interconnection layers 215. The base portion 211a and standing wall portion 21lb, which form the storage node 211, as well as the capacitor insulating film 212 and the cell plate 213 form a cylindrical stacked type capacitor 210 for accumulating the charges corresponding to the data signal. The base portion 211a and the standing wall portion 21lb, which form the storage node 211, are formed of polysilicon layers. The capacitor insulating film 212 is formed, e.g., of a nitride film. The cell plate 213 is formed of a polysilicon layer.
FIGS. 38-51 are cross sections showing a manufacturing process (first-fourteenth steps) of the DRAM shown in FIG. 37. Referring to FIGS. 37 and 38-51, the manufacturing process of the conventional DRAM will be described below.
First, as shown in FIG. 38, the element isolating oxide film 202 is formed on the predetermined region of the major surface of the silicon substrate 1 by an LOCOS method.
Then, as shown in FIG. 39, a thermal oxidation method is used to form she gate oxide film 205, and then the gate electrodes (word lines) 204b, 204c, 204d and 204e are selectively formed. The insulating film 207 covering the gate electrodes 204b-204e are formed by two oxide film forming steps and two etching steps. The gate electrodes 204b, 204c, 204d and 204e covered with the insulating film 207 are used as a mask for ion implantation, by which impurity is ion-implanted into the surface of the silicon substrate 201. Thereby, the source/drain regions 206a, 206b, 206c and 206d are formed.
Then, as shown in FIG. 40, a high-melting point metal layer, e.g., of tungsten, molybdenum or titanium is formed and then is patterned into a predetermined shape. Thereby, the buried bit line 208 directly connected to the source/drain region 206a is formed. The insulating film 209 is formed to cover the buried bit line 208.
As shown in FIG. 41, a CVD method is used to form a polysilicon layer 211c doped with impurity on the whole surface of the silicon substrate 201.
As shown in FIG. 42, the polysilicon layer 211c is covered with an insulating layer 235 formed of, e.g., silicon oxide film (SiO.sub.2). The thickness of this insulating layer 235 determines the height of the standing wall portion 21lb which forms the storage node (the lower electrode of the capacitor).
As shown in FIG. 43, resist (not shown) is applied to the surface of the insulating layer 235, and lithography is used to pattern the same into a predetermined shape. Thereby, a resist pattern (capacitor insulating layer) 236 is formed. The width of the resist pattern 236 determines the space between the adjacent capacitors.
As shown in FIG. 44, the resist pattern 236 is used as a mask for applying anisotropic etching, by which the insulating layer 235 is selectively removed. Thereafter, the resist pattern 236 is removed.
As shown in FIG. 45, the CVD method is used to form a polysilicon layer 211d containing the impurity on the whole surface. The thickness of this polysilicon layer 211d is smaller than the thickness of the polysilicon layer 211c formed thereunder.
As shown in FIG. 46, a thick resist 237 is formed to cover the whole surface of the polysilicon layer 211d. Etchback is applied the resist 237 to expose the polysilicon layer 211d covering the upper surface of the insulating layer 235.
As shown in FIG. 47, the etching is applied to the exposed polysilicon layer 211d (see FIG. 46), and subsequently the etching is applied to the insulating layer 235 (see FIG. 46) in a self-aligned manner to remove the same. Thereby, the surface of the polysilicon layer 211c is partially exposed. Also, the standing wall portion 211b forming the storage node 211 is completed.
As shown in FIG. 48, the exposed polysilicon layer 211c (see FIG. 47) is removed in a self-aligned manner by the anisotropic etching. Thereafter, the resist 237 (see FIG. 47) is removed. Thereby, the base portion 211a forming the capacitor lower electrode (storage node) 211 is completed. Thus, the capacitor lower electrode (storage node) 211 formed of the base portion 211a and the standing wall portion 21lb is completed.
As shown in FIG. 49, the thin capacitor insulating film 212 formed of, e.g., a silicon nitride film is formed on the surface of the capacitor lower electrode 211.
As shown in FIG. 50, the cell plate 213 made from electrically conductive polysilicon is formed on the whole surface. Thereby, the stacked type capacitor 210, which includes the base portion 211a and standing wall portion 21lb forming the capacitor lower electrode 211 as well as the capacitor insulating film 212 and cell plate 213 is completed.
As shown in FIG. 51, the cell plate 213 is covered with the thick innerlayer insulating film 214. The interconnection layer 215 of, e.g., aluminum having a predetermined shape is formed on the surface of the interlayer insulating film 214.
Finally, as shown in FIG. 37, the surface of the interconnection layer 215 is covered with the protection film 216. By the foregoing steps, the memory cells of the conventional DRAM are formed
As stated before, in the conventional DRAM, the standing wall portion 21lb, which forms the cylindrical capacitor lower electrode (storage node) 211, is made of polysilicon.
The polysilicon generally has microscopical unevenness on its surface. FIG. 52 is an enlarged view of a portion of the polysilicon layer 211d indicated by A in the manufacturing step of FIG. 45. Referring to FIG. 52, the polysilicon layer 211d formed on the side surface of the insulating layer 235 has the surface roughness of about 1/10 of its thickness. For example, if the polysilicon layer 211d has the thickness of 1000 .ANG., its surface 300 has the roughness of about 100 .ANG.. The unevenness of the surface of the polysilicon layer 211d is caused by the grain boundary. More specifically, the polysilicon layer 211d includes silicon crystal grains having different grain diameters in a range from about 200 .ANG. to about 500 .ANG.. Therefore, the crystal grains have different growth tales, and thus some grains grows more rapidly than others. As a result, the microscopical unevenness is formed in the upper surface of the polysilicon layer 211d.
Referring to FIG. 37, in a macroscopical view, the cell plate 213 has an angular end 213a which is formed on a surface of a bent portion of the standing wall portion 211b with the capacitor insulating film 212 therebetween. FIG. 53 is an enlarged cross section showing a portion B of the DRAM shown in FIG. 37. Referring to FIG. 53, the end 213a of the cell plate 213 opposed to the bent portion 301 of the standing wall portion 211b 301 has a protruding shape.
As stated above, in the prior art, the surface 300 of the standing wall portion 211b microscopically has the unevenness (see FIG. 52), and the end 213a of the cell plate 213 macroscopically has the protruding shape (see FIG. 53). The microscopically uneven surface 300 of the standing wall portion 211b and the macroscopical protruding end 213a of the cell plate 213 disadvantageously reduce the durability of the capacitor insulating film 212 in the prior art. More specifically, the microscopical unevenness of the surface 300 of the standing wall portion 211b causes irregular electric field applied to the capacitor insulating film 212, resulting in reduction of the durability of the insulating film. Further, the electric field is concentrated at the end 213a of the cell plate 213, which also reduces the durability of the capacitor insulating film 212.